The present invention relates to a technique for diagnosing a semiconductor integrated circuit (IC) and a technique effective for application to a technique for detecting defective bits in a semiconductor memory. The present invention relates to, for example, a technique effective for use in a semiconductor integrated circuit in which a semiconductor memory, and a test circuit for the semiconductor memory, i.e., a test pattern generator for generating each test pattern are incorporated.
A system for diagnosing a semiconductor memory such as a semiconductor memory device or the like is carried out by a test device called xe2x80x9cmemory testerxe2x80x9d. The memory tester generates test pattern data, and supplies the test pattern data to a semiconductor memory to be tested to thereby write the data into the corresponding memory cell of the semiconductor memory. Thereafter, the data written into the memory cell is read into the memory tester, and the read data and an expected value held within the memory tester are compared, whereby the semiconductor memory is diagnosed.
A procedure for developing a semiconductor memory is performed as shown in FIG. 11. The design of a system is carried out based on specifications of the semiconductor memory to be developed. Further, specific circuit design is performed based on the system design. Various photomasks necessary for the fabrication of the semiconductor memory are produced. Thereafter, a wafer having a plurality of semiconductor memory circuits formed thereon is manufactured through a wafer process in a semiconductor manufacturing process by utilizing the photomasks, and the wafer is cut to a plurality of memory chips. Further, the respective memory chips are sealed with a sealing agent such as a resin, so that they are assembled into a package. A sample (also called xe2x80x9csample chipxe2x80x9d) is suitably extracted from the semiconductor memories assembled as the package, and the extracted sample is inspected by using the memory tester. Thus, the presence or absence of a faulty component lying within the sample can be detected.
When the faulty component is found out, the result of testing on the sample regarded as the faulty component is analyzed to find out the cause of the failure. In order to avoid the failure, redesign such as system design, circuit design or layout design or the like for the semiconductor memory is carried out. A wafer formed with a plurality of semiconductor memory circuits is manufactured again through the wafer process in the semiconductor fabricating process, based on the redesigned data. The execution of a retest is repeated by the memory tester. The development of the semiconductor memory has been regarded as completed at a stage in which no failure is detected upon testing.
However, in the diagnostic system for supplying the test pattern data generated from the memory tester to the corresponding semiconductor memory as described above, various semiconductor integrated circuit devices (also called xe2x80x9cICxe2x80x9d) constituting the tester have been manufactured by a manufacturing or production processing technique antecedent to one generation or a few generations as compared with the generation of each. semiconductor memory to be checked. Namely, the minimum values of the fabrication processing dimensions of the respective semiconductor integrated circuit devices constituting the tester are set thicker than those of the semiconductor memory to be checked. Thus, a next-generation or new-generation semiconductor memory is checked or examined by the memory tester comprised of the previous-generation semiconductor integrated circuit devices. Therefore, specifications such as an operating speed, etc. necessary for a memory tester for examining the new-generation semiconductor memory would become very strict. In order to achieve a desired test speed, a plurality of semiconductor integrated circuits respectively having the same function are prepared within the memory tester. A contrivance to make the test speed faster is made by, fore example, constructing a system so that the semiconductor integrated circuits can be parallel-processed. As a result, the memory tester is accompanied by a problem that the system becomes complex in configuration and the size thereof would become inevitably large.
In a logic semiconductor integrated circuit device or the like on the other hand, a logic simulation using a work station is performed at a stage of circuit design and system design prior to a wafer process in a semiconductor manufacturing process and wafer fabrication. Further, a technique for detecting failures in advance has been established. Therefore, the test procedure of the logic semiconductor integrated circuit device has an advantage in that the total interval required to develop it would become short as compared with the test procedure of the aforementioned semiconductor memory, for manufacturing each semiconductor-chip (also called xe2x80x9creal chipxe2x80x9d) corresponding to an actual product and testing it.
However, since test patterns necessary for a logic simulation are different from each other every logic semiconductor integrated circuit devices, much time is required to form the test patterns. Further, there is also inconvenience that since the test patterns are long in the number of steps, the time required to test the real chip becomes long as compared with the test on the real chip by the tester, thereby making it impossible to substantially execute the test.
There may be cases where in the semiconductor memory on the other hand, the numbers of bits of addresses and data simply differ from each other even in the case of the development of a new product and thereby most of generation programs for test patterns do not stand in need of changes. There may be also cases in which the know-how to analyze failures, which has been built up till now, can be utilized. Therefore, it has been tested by the memory tester after the sample chip has been manufactured as described above.
However, the above-described development procedure has a problem in that although the load on the design is small, the time required between redesigning the memory circuit and fabricating the chip once a failure occurs, greatly increases, so that the period for the development of the semiconductor memory would become long.
Further, the above-described developing system has a problem in that since the recent semiconductor memory is complex in its timing condition from a demand for speeding up and a demand for the achievement of an increased or advanced function such as a pipeline operation as in the case of a synchronous dynamic random access memory (hereinafter also called xe2x80x9cSDRAMxe2x80x9d), a mistake in its design increases and the period for its development becomes long increasingly.
On the other hand, a verifying tool, which has allowed the generation of a test pattern matched with a product""s operation with an operating level from an EDA (Engineering Design Automation) bender, has been announced. One example thereof is a verifying tool called xe2x80x9cVisualTestxe2x80x9d by TSSI Co., Ltd. In the present verifying tool, a procedure for generating each test pattern is inputted in flowchart form by using a workstation or the like, whereby a semiconductor memory represented by circuit design data can be checked. A memory development procedure at the time that the present verifying tool is used, is illustrated in FIG. 12. Incidentally, FIG. 12 has been considered by the present inventors and is not known to date.
As shown in FIG. 12, verification is made using the present verifying tool without fabricating a wafer so that a failure or defect can be detected, whereby an advantage is brought about in that the development period can be greatly reduced.
However, the above-described method needs to create a test pattern as a pattern data file because the verifying tool is a logic verifying tool (logic simulator) called xe2x80x9cVerilogxe2x80x9d even if an operating level could be described on xe2x80x9cVisualTestxe2x80x9d. Since the test pattern for the semiconductor memory is massive (ranges from a few giga steps to a few mega steps), it is extremely difficult to execute comprehensive verification. There is an extremely high possibility that this will remain at a partial simulation in practice.
On the other hand, the present inventors have discussed a technique called virtual tester to improve a method for testing the semiconductor memory, the logic semiconductor integrated circuit device, etc. This virtual tester technique is not known to date.
The virtual tester considered by the present inventors includes a pattern generator and a simulator. The pattern generator is described in the form of a program capable of being executed on a computer and generates a test pattern for each semiconductor memory in accordance with a predetermined algorithm. The simulator checks for a semiconductor memory on the computer according to the test pattern formed by the pattern generator when logic design data for the semiconductor memory is given thereto.
It is however considered that since the test pattern formed by the pattern generator must be retained in a memory device even in the case of the diagnostic method using the virtual tester, a normal computer system is short of storage capacity and a checking time interval will increase.
On the other hand, a hardware emulator using an FPGA (Field Programmable Gate Array) is known as a method for speeding up logic verification. The hardware emulator is a tool for electrically making a logic configuration of a logic circuit described in an HDL (Hardware Description Language) by using the FPGA and verifying its logic operation from an electrical operation thereof. Since the hardware emulator actually generates a test pattern for each step and verifies it as distinct from the logic simulator such as Verilog, it is not necessary to prepare the test pattern as a file. Therefore, a high-capacity memory device becomes unnecessary. Since the hardware emulator is hardware constructed of an actual electric circuit, it can perform verification faster than the-logic simulator by a few hundred to a few thousand times. It is therefore considered that comprehensive verification is made possible by combination with the HDL description of the semiconductor memory.
The present inventors have paid attention to the fact that in a tester, a test pattern generator called ALPG (Algorithmic Memory Pattern Generator) for generating a test pattern for each memory in accordance with a predetermined algorithm is constructed of a logic circuit relatively small in scale and can be described by the HDL, and a technique for developing the HDL description into an IC has been established. The present inventors have carried out an extensive investigation while an idea is being obtained that it might be loaded into a memory chip by further scaling down a hardware scale and a logic circuit scale of the ALPG employed in the tester. As a result, as will be described later, the present inventors have believed firmly that a semiconductor memory equipped with a test circuit can be implemented by adopting the architecture of the ALPG capable of scale down, thus leading to the application of the present invention.
Incidentally, Japanese Patent Application Laid-Open No. Sho 56-169292 is known as a technique for testing a semiconductor memory. Japanese Patent Application Laid-Open No. Sho 56-169292 discloses a technique for writing test data into memory cells while automatically updating each address by an address counter provided over a memory chip, and thereafter reading and verifying the written test data, thereby checking for all the memory cells.
However, in the system wherein the testing address counter is provided on the memory chip, such an all xe2x80x9c1xe2x80x9d decision or an all xe2x80x9c0xe2x80x9d decision that data xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d is written into all the memory cells and thereafter the written data is read and checked, can be performed with efficiency. However, there are known a marching test and an N2 pattern test as memory tests in addition to the all xe2x80x9c1xe2x80x9d decision and the all xe2x80x9c0xe2x80x9d decision. A high-accuracy result of diagnosis cannot be obtained unless these are carried out. The address counter-contained system is considered to have a problem that it carries out limited types of decisions alone and thereby a check remains incomplete as it is.
In order to cause the tester to test a memory unit in a semiconductor integrated circuit (logic integrated circuit with a built-in memory) wherein a peripheral logic (logic circuit) is formed over a single semiconductor chip together with the memory (memory unit), a serial/parallel conversion circuit is provided at an input/output portion of the memory. In this case, the serial/parallel conversion circuit and the tester are connected to each other by serial communications during a test period. Thus, a test pattern given in serial form, which is outputted from the tester, is inputted to the memory unit through the serial/parallel conversion circuit. The serial/parallel conversion circuit converts the input test pattern of serial form into parallel data, followed by writing into the memory unit as test data. Thereafter, the data written into the memory unit is read and the read data is converted into serial data, followed by outputting to the outside of the chip. According to this system, there is an advantage that the tester can be utilized and the number of external signal terminals (pins) for inputting the test pattern can be saved for the semiconductor integrated circuit. However, a problem arises in that a test time interval would become long by the time required to perform the serial/parallel conversion.
An object of the present invention is to provide a semiconductor memory diagnostic technique capable of diagnosing a semiconductor memory without manufacturing a real chip.
Another object of the present invention is to provide a memory diagnostic technique capable of shortening a period necessary for the development of a new semiconductor memory.
A further object of the present invention is to. provide a semiconductor memory diagnostic technique capable of performing diagnoses based on various decision methods for an internal memory without having to use an external tester.
A still further object of the present invention is to provide a memory checking method capable of diagnosing a semiconductor memory in a short time.
A still further object of the present invention is to provide a semiconductor memory capable of being diagnosed without providing external terminals (pins) for inputting test patterns and in a short time.
The above, and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
A summary of a typical one of the inventions disclosed in the present application will be explained as follows:
Namely, a data processing unit used as a test circuit capable of generating a predetermined test pattern according to a command is provided over a semiconductor chip equipped with a memory circuit.
A data processing unit (10) includes,
a microprogram controlled control unit (11, 12 and 13) capable of generating a test pattern (addresses and data) for a memory circuit in accordance with a predetermined algorithm and executing control for performing the reading of written data, an address arithmetic unit (14) whose operation is controlled by the control unit and which generates an address to be supplied to a decoder of a memory,
a data arithmetic unit (15) whose operation is controlled by the control unit and which generates data to be written into each memory cell to be checked, and
a data determination circuit (16) which determines the read data and outputs the result of determination therefrom. The data processing unit (10) does not need to be provided as a dedicated test circuit and is available even for other applications.
The control unit has a command or instruction memory for storing a plurality of commands using the already-existing tester language and a test language. A test pattern (addresses and data) is generated according to the predetermined algorithm defined by the plurality of commands. The tester language can be regarded as an effective instruction or command language for efficiently generating each test pattern including the addresses and data. The tester language is called language generally used in the tester industry and may be used as, for example, a language compatible with a tester language developed by Advantest Co., Ltd. The language descriptive of the predetermined algorithm is not necessarily limited to the tester language. If a command language capable of generating a test pattern including addresses and data is used, then it will be enough for the above language.
The instruction memory can be selected from the already-existing memories such as a dynamic random access memory, a static random access memory, a read only memory, an electrically programmable non-volatile memory device, or an electrically programmable and erasable non-volatile memory device, etc.
The instruction memory may be formed of a non-volatile memory circuit including electrically programmable and electrically erasable non-volatile memory cells, e.g., a flash memory. Thus, the plurality of commands defining the predetermined algorithm is held even in a state in which a circuit""s source potential is not supplied. A plurality of commands defining a desired algorithm can be retained in a non-volatile memory cell by rewriting data stored in a non-volatile memory cell as needed. Thus, test patterns can be intentionally changed ever memory products and lots. This is concerned with an increase in the efficiency of a memory check or inspection where specific failure or defect generation patterns can be analogized every products and product lots.
A memory circuit to be checked is defined as the already-existing memory such as a dynamic random access memory, a static random access memory, a read only memory, an electrically programmable non-volatile memory device, or an electrically programmable and erasable non-volatile memory device or the like.
It is desirable to cause the test circuit to have a self-checking function for performing a logic inspection of the test circuit itself.
The semiconductor integrated circuit including the memory circuit includes a redundant circuit having a spare memory row or a spare memory column capable of be replaced by a defective bit, which is provided in the neighborhood of the memory circuit. In this case, the control unit is provided with a self-repairing circuit. The self-repairing circuit has an algorithm for selecting the most suitable spare memory row or spare memory column, based on the result of determination by the data determining means and replacing the defective bit with the selected one and performs address conversion for the replacement of the defective bit in accordance with the algorithm.
Further, in a semiconductor integrated circuit wherein a peripheral logic circuit (logic circuit) is formed over one semiconductor chip together with a memory circuit, the test circuit is constructed so as to have the function of being capable of generating not only a test pattern for a memory unit but also a test pattern for peripheral logic.
According to the above means, diagnoses based on various decision or determination methods can be done without having to use an external tester. It is also unnecessary to provide external terminals (pins) for inputting each test pattern. Further, since the test circuit formed over the same semiconductor chip as the semiconductor memory is constructed of a logic circuit formed by the same manufacturing technology, i.e., the same generation semiconductor process technique as the semiconductor memory, substantially the same operating speed as the semiconductor memory to be tested can be easily implemented. Thus, according to the present invention, the memory can be diagnosed in a short time. Since the parallel processing using the plurality of the same circuits described above becomes unnecessary, the test circuit itself can be reduced in logic scale and circuit scale as compared with the memory tester. Since the test circuit itself is small in logic scale and circuit scale, the formation of the test circuit in on-chip form can be implemented with relative ease.
In order to improve the yield of production of the test circuit portion, wire processing dimensions of the portion of the test circuit may be set larger than those of each memory cell in the memory unit. Thus, the probability that the test circuit portion will become faulty, can be reduced.